Data transmission is an important function in many integrated circuit devices. As bandwidth requirements of wire-line and wireless transceiver systems becomes stringent, a sampling clock generator is a significant component as it produces critical clocking signals.
However, conventional time-interleaved (TI) analog-to-digital (ADC) circuits require significant area and power, and may suffer from high jitter and clock timing skew. Conventional TI ADCs may use a phase interpolator or a delay-locked loop for multiple phase clock generation, each of which has disadvantages. While a phase interpolator based clock generator is suitable for high-speed operation, it consumes large power and area. A delay-lock loop based TI ADC may have a small size compared with phase interpolator based TI ADC, but does not provide a good architecture for high-speed operation because a phase detector offset and delay mismatch between the delay cells may result in non-linearity that can limit operation speed.
Accordingly, circuits and methods that implement an analog-to-digital converter that reduce size, power consumption and noise, and also enable high speed operation are beneficial.